Open source TDC core for FPGAs


TDC core block diagram

Recently, I have been working on a time to digital converter (TDC) core for Xilinx Spartan-6 FPGAs. I was contracted by CERN to develop it, and everything is available under the LGPL license from their open hardware repository.

The reasons for using the FPGA-based solution compared to the ASICs available on the market are flexibility (e.g. channel count), low latency (which enables applications such as fine delay generators that they cannot do with the current chips), low cost, more sourcing possibilities, and increased openness.

I still need to test the core on real hardware and precisely characterize its parameters, but you can already download the source and read the documentation. TDCs are useful even outside the context of large particle accelerators, for example in LIDARs and laser rangefinders.

Comments are closed.