Archive for October, 2010
Just a quick note to inform you that the project will be exhibited and quickly presented during BLIT on November 6th in Potsdam (near Berlin). See you there if you are around!
Get the original video from Free Electrons.
Upgrade your board now to the latest version of MM SoC that brings significant improvements:
- Extensive Navré core testing – re-using the Python-based test suite from simulavr
- Navré bugfixes – as a consequence of the aforementioned testing
- Wishbone burst support in L2 cache for faster memory access from CPU
- Partial crossbar Wishbone switch, solves Ethernet FIFO overflow problems when CPU is running from flash
- LM32 JTAG debugger support (Michael Walle). We can now use OpenOCD to debug the system live!
- Support for USB input devices (mouse + keyboard). USB bugs remain, but it’s becoming to be usable.
- Text console in BIOS and demo firmware – use them standalone without a serial terminal. Only German USB keyboard layout supported at the moment.
- MIDI THRU support
- New memory map (Michael Walle)
- New flash map to support the multiple bitstreams and the rescue mode
- Standby and rescue bitstreams. After power is applied, the board is in standby mode. Press the middle pushbutton (#2) to boot it. If pushbutton #1 is pressed at the same time, rescue mode will be enabled.
- ICAP write support – we’re not doing partial reconfiguration with it, only reboot the FPGA back to the standby bitstream
- Fixed DDC EDID read, now works reliably with all monitors
- Reduced frequency to 80MHz – we’ll try to increase it when Xilinx fixes its software
- Memory tester core
- Board revision readout
- Fixed SDRAM reset bug – now the I/O calibration no longer randomly fails after a reset
- Code cleanups