Implementing an OHCI host controller is not a straightforward task. The USB protocol is quite complex – making full hardware implementations difficult and inefficient – and its polled nature would put a heavy burden on a CPU if it were all implemented in software. The OHCI specification also makes things worse with regards to the controller’s complexity, by offloading a lot of work to the controller hardware.
An hybrid solution, dubbed “softusb”, was therefore chosen. The USB controller includes a small dedicated microprocessor that runs a software version of an OHCI-compliant USB host stack. Only the parts that need very precise timing – namely data serialization and deserialization – is fully implemented in hardware. It is noteworthy that this approach enables switching between a host and a device controller by simply replacing the microprocessor’s program (and adding the appropriate pull-up/pull-down resistors on the D+/D-).
After unsuccessful experiments with ZPU which turned out to be extremely slow and realizing that all other open source small microprocessors were in general very bad, I ended up designing my own AVR compatible core called Navré.
The Navré core is built on the same 2-stage pipelined architecture as the original AVR, and also executes most instructions in one cycle. On Spartan-6 technology, it occupies about 400 LUTs and can run at speeds between 60MHz and 85MHz (depending on the memory configuration), well above the 48MHz clock used for USB. As far as I know, this makes it the fastest and smallest 8-bit open source microprocessor on the planet, which runs code one order of magnitude faster than ZPU and does not waste FPGA resources on a 32-bit datapath which is not really needed for the USB application. The Navré source code is extremely simple, with less than 700 lines of self-contained Verilog HDL.
Currently, all “minimal core” instructions are implemented, and “classic core” instructions are being worked on so that Navré will have full C compiler toolchain support enabling the efficient development of the USB stack. More work should also go in the validation of the core, perhaps using a test suite similar to that of simulavr. Nonetheless, it is capable today of running correctly small C and assembler programs such as the recursive computation of Fibonacci numbers.
The Navré core uses on-chip RAM to store its program (loaded by the main CPU of the SoC) and data. The data memory is shared with the main SoC CPU, and will be used to store the OHCI descriptors and data. It sports a 32-bit interface on the SoC side to enable high bandwidth transfers of USB data without hogging the main CPU’s time.
NB: I will be looking shortly for a USB protocol analyzer to assist me with the debugging of the OHCI stack. If you happen to sell or lend one or know where I could get one for cheap, let me know. Thanks!