Lately, I have had access to a computer with the Cadence RTL Compiler and the TSMC 90nm standard cell libraries to play with, so by curiosity I tried to run synthesis of the LatticeMico32 core.
The most interesting result is that it’s RIDICULOUSLY FAST. It nearly meets timing at 800MHz, which is 7-8 times the speed on Virtex-4. Power consumption is 29mW only at this frequency. Area is very small, with only 13K cells used (0.081 square millimeters).
If I did not do a mistake using the synthesizer (since it gets approximately the same number of flip-flops as in the FPGA implementation it’s probably correct) and if these results are for real, they definitely make me want to leave FPGAs and do ASICs instead 
The LM32 configuration is the same as the one used on ML401, except that I disabled the caches because the synthesizer apparently does not support RAM extraction and generated a mess of flip-flops instead.
Those results were obtained from the gate-level netlist only, with a wire load model. I did not try to lay out the core in silicon.
(original post with synthesis script and detailed reports)